1. Field of the invention
The present invention relates to a circuit for synchronizing a serial input signal with a clock signal, and more particularly to such a synchronous circuit for generating a detecting signal in response to the serial input signal to enhance the immunity from signal malfunctions that may occur, because the detecting period of the received signal is changed due to the change of the reference frequency, i.e. the change in the period or frequency of the clock signal according to the variation of the temperature or the ambient environment.
2. Related Art
A conventional circuit for synchronizing a serial input signal generates output signals synchronized with the initial rising of a serial in the serial input signal, or just in the case where the serial input signal itself rises.
A conventional circuit for synchronizing the serial input signal to output a synchronized serial input signal and detecting signal to detect the received input signal is shown in FIG. 1 and includes a synchronous circuit 1 for synchronizing a serial input signal P2 according to a clock signal P.sub.1 to provide a synchronized serial input signal P3. A reset circuit 2 outputs a reset signal P4 according to the output of the synchronous circuit 1. A frequency divider circuit 3 generates a detecting signal P5 by dividing the reference frequency of the clock signal P1 according to the reset signal P4 output from the reset circuit 2.
The synchronous circuit 1 receives the clock signal P.sub.1 and serial input signal P2. The synchronous circuit 1 synchronizes the serial input signal P2 with a rising edge of the clock signal P1, and outputs the serial input signal P3. The synchronized serial input signal P3 is input to the reset circuit 2 and the reset signal P4, synchronized with the initial rising edge of the synchronized serial signal P3, is output.
As shown in the waveform of FIG. 2(D), the reset signal P4 is still at high level. Reset signal P4 is supplied to the frequency divider circuit 3 to which the clock signal P1 is also input.
The frequency divider circuit 3 begins to operate when the rising edge of reset signal P4 is detected and divides the reference frequency of the clock signal P1 and then outputs the detecting signal P5 that is necessary for detecting the synchronized serial input signal P3.
The synchronized serial input signal P3 is output after being synchronized in the synchronous circuit 1 when the clock signal P1 and received serial input signal P2 are input to the synchronous circuit 1 as shown in FIGS. 2(A) and 2(B), and is synchronized at a rising edge of the signal, when the serial input signal P2 is input and the clock signal P1 is at a high level for the first time, and then output as shown in FIG. 2(,C).
The synchronized serial input signal P3 is input to the reset circuit 2, and the reset signal P4 is output as shown in FIG. 2(D). This reset signal P4 is synchronized at the initial rising edge of the synchronized serial input signal P3 and then supplied as a reset signal to the frequency divider circuit 3.
According to the operational waveforms of FIGS. 2(A)-2(B), showing the operation of the circuit of FIG. 1, an initial pulse of the first serial input signal P2 is used after being synchronized at the rising edge of the clock signal P1, and therefore the detecting signal P5 that is output by inputting the clock signal P1 and reset signal P4, when the reference frequency of the clock signal P1 changes in accordance with the ambient environment or other changing condition, changes according to the variation of the frequency of the clock signal P1.
Thus, if the synchronized serial input signal P3 was detected when the detecting signal P5 changes from being at a high level to a low level, the frequency of the detecting signal P5 would be changed according to the change in the frequency, and therefore, erroneous data different from the serial input signal is input to a receiving stage (not shown).
The following description relates to the case where the detecting signal P5 is output as shown in FIG. 2(F) in the case where the reference frequency of the clock signal P1 is changed by the variance of the ambient environment or temperature.
When the serial input signal P2 is input as shown in FIG. 2(B), "1110001" is output as the value of the received signal, from the detecting signal and the synchronized serial input signal, at the time of changing the detecting signal P5 from the high level to the low level unless there is a change in the detecting period. However, in the case where the detecting signal P5 that is output when the period of the clock signal P1 increases due to the change of the frequency is output as shown in FIG. 2(F), the value of the received signal becomes "1110011". That is because "0", the signal value output at the 6th filling edge after the detecting signal P5 is synchronized, is falsely recognized as a "1".
When the detecting signal P5 output by the frequency divider 3 is output as in the detecting signal P5 because the period of the reference frequency decreases, the value of the received signal detected from a receiving stage is "1110000", and in this case, "1", the value of the 7th falling edge b after synchronizing the detecting signal P5, is falsely recognized as a "0".
As described above, when the reference frequency is changed by the variation of the ambient environment and/or temperature, the period of the detecting signal changes, and as a predetermined time passes, the period thereof becomes delayed. Therefore a signal detected by the detecting signal is erroneous, as the period of the detecting signal increases continuously.
Such a case represents a fatal malfunction to a receiving device using a digital signal, and the variation of the ambient environment becomes a critical factor in designing circuits thereby setting a limit to the selection of the devices. Accordingly, the synchronizing and detecting circuits become complex and increase in size.
In an oscillating circuit using an inductor L or a capacitor C for generating the reference frequency signal, the oscillating frequency of the inductor L and capacitor C is easily changed by environmental conditions such as the temperature, humidity or air-pressure, or by long-time use. Therefore a phase-shift type oscillating circuit or a tuning type oscillating circuit cannot be used. A crystal oscillating circuit with high oscillating frequency stability must be used, which, however results in increased manufacturing costs.